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Job Title: Senior Layout Designer<\/p>\n
Location:\u00a0Austin, TX (On-site, 5 days a week)
Job Type:\u00a0Full-time, Permanent
Work Authorization:\u00a0H1B Sponsorship Available
Compensation:\u00a0USD 180000 – 200000
Schedule:\u00a0Standard day shift (on-site only)
Experience Level:\u00a0Senior (10 plus years required)<\/p>\n
About the Role<\/p>\n
We are seeking a highly experienced Senior Analog Mixed Signal Layout Engineer to join a world-class design team working on next-generation high-performance ADC, DAC, SerDes, and advanced mixed-signal solutions. This role directly impacts cutting-edge silicon development across advanced CMOS, FinFET, and GAA process nodes.<\/p>\n
This is an on-site position in Austin, Texas. Candidates must demonstrate strong job stability and a proven track record in high-speed analog layout design.<\/p>\n
Key Responsibilities<\/p>\n
Own the physical layout design of high-performance ADC, DAC, SerDes, and analog\/mixed-signal circuits across 2nm to 16nm technology nodes.
Plan and implement layouts for high-speed, low-noise analog blocks, ensuring signal integrity, device matching, symmetry, and optimal parasitics.
Collaborate closely with circuit design teams to meet aggressive PPA targets while following DFM best practices.
Perform layout design, verification, and integration using Cadence Virtuoso and Synopsys tools.
Drive floorplanning and analog block partitioning, including power grid design, guard ring placement, and substrate isolation.
Work with foundry and CAD teams to optimize mixed-signal design flows for FinFET and GAA technologies.
Conduct LVS, DRC, ERC, and PEX reviews and close verification loops.
Support top-level integration and tape-out, ensuring all layout data meets signoff requirements.
Provide mentorship and help define layout methodologies, automation improvements, and best practices.
Minimum Qualifications<\/p>\n
10 plus years of industry experience in analog\/mixed-signal layout for advanced nodes (2nm to 16nm; TSMC preferred).
Proven experience designing layouts for high-speed ADC, DAC, and SerDes circuits.
Strong knowledge of matching, shielding, EM constraints, timing, and high-speed layout techniques.
Hands-on experience with Cadence Virtuoso (Layout, XL), PVS, Quantus, and the complete schematic-to-layout flow.
Experience with FinFET and\/or Gate-All-Around process technologies.
In-depth knowledge of analog layout structures including differential pairs, current mirrors, resistors, capacitors, guard rings, bias networks, and ESD structures.
Prior leadership in tape-out processes, design documentation, and cross-functional coordination.
Masters degree in Electrical Engineering, Computer Engineering, or related field.
Strong job stability with consistent, long-term employment history.
Preferred Qualifications<\/p>\n
Experience with Mentor Siemens Calibre for verification.
Scripting skills in SKILL, Python, or Tcl for layout automation.
Exposure to floorplanning and top-level integration for complex mixed-signal SoCs.
Understanding of SI, IR drop, electromigration, and thermal effects in high-speed designs.
Why Join Us<\/p>\n
Work on industry-leading high-speed data and optical communication silicon.
Hands-on experience with the most advanced TSMC process technologies including FinFET and GAA.
Contribute across the entire silicon lifecycle from floorplanning to tape-out.
Competitive compensation and meaningful equity package.
Full medical and dental benefits.
A fast-paced, innovative environment that rewards technical ownership and excellence.<\/p>\n
Pay: $180,000.00 – $200,000.00 per year<\/p>\n
Lugar de trabajo: En persona
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