Descrizione del lavoro:
Location: Austin, Texas (Onsite, 5 days\/week)<\/p>\n
Industry: Semiconductor, AI Infrastructure, Cloud Hardware<\/p>\n
Salary: $170,000\u2013$200,000 USD + Equity (4-year vesting)<\/p>\n
Experience: 5\u20138 years (DFT specialization required)<\/p>\n
Visa: H1-B sponsorship available<\/p>\n
Skills \u2013 DFT Specification & Architecture, ATPG, MBIST, JTAG, Silicon Bring-up & Test (ATE), Scan Chains, DFT Compression, Logic BIST, EDA Test Tools (DFT Max, Tessent, Modus, SpyGlass, Design\/Fusion Compiler, TestKompress), IP Integration, ASIC Synthesis & Verification, Problem-Solving, Communication<\/p>\n
Summary<\/p>\n
Well-funded hardware startup (with $180MM in recent funding, backed by leading VCs) seeks an experienced DFT Engineer to innovate and own design-for-test (DFT) methodologies for advanced digital and mixed-signal SoCs. This hands-on role collaborates cross-functionally to define, implement, and deploy robust DFT strategies for next-generation programmable DSP chips powering the world\u2019s fastest AI and cloud infrastructure.<\/p>\n
Must-Haves<\/p>\n
5+ years in DFT spec, architecture, insertion, and analysis for complex silicon
Experience in silicon bring-up, debug\/validation of DFT on ATE, ATPG, MBIST, JTAG
ASIC DFT, synthesis, simulation\/verification know-how
Strong organizational\/problem-solving skills; detail oriented
Willing to work on-site in Austin, TX (Relocation not covered)<\/p>\n
Preferred<\/p>\n
Master\u2019s degree in Electrical Engineering
IP integration (memories, test controllers, MBIST, TAP)
Expert use of EDA tools: DFT Max, Tessent, Modus, Design\/Fusion Compiler, SpyGlass, TestKompress
Silicon test coverage improvement, hierarchical design\/test<\/p>\n
Responsabilit\u00e0<\/p>\n
Lead and implement SoC DFT architecture and ATPG\/MBIST strategy
Insert, validate, and debug all DFT logic \u2013 scan chains, BIST, boundary scan, TAP, compression, MBIST
Own silicon bring-up and ATE debug for new test features and DFT IP
Collaborate to improve test coverage, resolve RTL violations, and streamline test processes
Develop and maintain formal DFT documentation<\/p>","protected":false},"author":63,"featured_media":0,"template":"","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"pmpro_default_level":"","_promoted":"","_job_location":"Austin, TX","_application":"https:\/\/visasponsor.jobs\/api\/jobs\/72e2673d44ba4415a822dd4f092a66be\/Digital-Test-Engineer-%E2%80%93-Chip-Design","_company_website":"","_company_tagline":"","_company_twitter":"","_company_video":"","_filled":0,"_featured":0,"_remote_position":0,"_job_salary":"","_job_salary_currency":"","_job_salary_unit":"","_joinchat":[]},"job-types":[398],"class_list":{"0":"post-12781","1":"job_listing","2":"type-job_listing","3":"status-publish","4":"hentry","5":"pmpro-has-access","7":"job-type-h1-b"},"_links":{"self":[{"href":"https:\/\/kick-start.us\/it\/wp-json\/wp\/v2\/job-listings\/12781","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/kick-start.us\/it\/wp-json\/wp\/v2\/job-listings"}],"about":[{"href":"https:\/\/kick-start.us\/it\/wp-json\/wp\/v2\/types\/job_listing"}],"author":[{"embeddable":true,"href":"https:\/\/kick-start.us\/it\/wp-json\/wp\/v2\/users\/63"}],"wp:attachment":[{"href":"https:\/\/kick-start.us\/it\/wp-json\/wp\/v2\/media?parent=12781"}],"wp:term":[{"taxonomy":"job_listing_type","embeddable":true,"href":"https:\/\/kick-start.us\/it\/wp-json\/wp\/v2\/job-types?post=12781"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}