Descrizione del lavoro:
Work Type: Full-Time | Permanent | Onsite \u2013 Austin, TX (5 days a week)<\/p>\n
Experience Required: 5\u201310 Years (ASIC\/FPGA Design, RTL Development)<\/p>\n
Compensation: USD $150,000 \u2013 $200,000 + Equity (4-year vesting)<\/p>\n
Industry\/Domain: Semiconductor \/ Cloud & AI Infrastructure \/ DSP Solutions<\/p>\n
Job Overview<\/p>\n
We are seeking talented and experienced VLSI RTL Designers \/ Micro-Architects to join a fast-growing semiconductor innovator in Austin. In this role, you will design highly sophisticated communication systems from the ground up, contributing to next-generation DSP (digital signal processing) solutions that power AI and cloud data center connectivity.<\/p>\n
Key Responsibilities
Translate high-level algorithmic requirements into efficient hardware implementations.
Interpret and apply protocol specifications (e.g., Ethernet 100G+).
Drive all design stages: micro-architecture definition, RTL coding (Verilog\/SystemVerilog\/VHDL), synthesis-friendly coding, timing-aware design.
Collaborate cross-functionally with:
Verification teams \u2013 testbench development, debug, coverage closure.
DFT teams \u2013 scan insertion, ATPG, BIST integration.
Physical design teams \u2013 floorplanning, timing closure, routing feedback.
Perform synthesis and timing analysis, generate SDC constraints, and debug functional\/timing issues.
Optimize RTL for area, power, and performance (PPA).
Maintain detailed design documentation (micro-architecture specs, interface docs).
Contribute to IP\/SoC integration and handle system-level interfaces.
Support silicon bring-up and validation (preferred).
Stay updated on EDA tools, CDC, linting, and formal verification methodologies.<\/p>\n
Must-Have Skills & Qualifications<\/p>\n
Minimum 5 years of experience in ASIC\/FPGA design.
Strong Verilog\/SystemVerilog expertise.
Proficiency in simulation tools, verification methodologies.
Strong teamwork, interpersonal, and problem-solving skills.
BS\/MS in EE\/CE from a leading institution.
Willingness to work on-site in Austin, TX, five days a week.<\/p>\n
Preferred Skills & Attributes
Background in:
Clock\/Voltage domain crossing, Low Power Design, DFT.
DSP-oriented design blocks.
Ethernet (100G and above).
Scripting experience in Python, Perl, TCL.
Experience with optical communication systems (a plus).<\/p>\n
Additional Information<\/p>\n
Visa: Open to sponsor H1-B.
Medical & Dental: Full coverage.
Relocation Expenses: Case-by-case basis.<\/p>","protected":false},"author":63,"featured_media":0,"template":"","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"pmpro_default_level":"","_promoted":"","_job_location":"Austin, TX","_application":"https:\/\/visasponsor.jobs\/api\/jobs\/4cae728e52254efa82f5246d144080de\/RTL-Logic-Design-Engineer-%E2%80%93-High-Speed-Interfaces","_company_website":"","_company_tagline":"","_company_twitter":"","_company_video":"","_filled":0,"_featured":0,"_remote_position":0,"_job_salary":"","_job_salary_currency":"","_job_salary_unit":"","_joinchat":[]},"job-types":[398],"class_list":{"0":"post-12785","1":"job_listing","2":"type-job_listing","3":"status-publish","4":"hentry","5":"pmpro-has-access","7":"job-type-h1-b"},"_links":{"self":[{"href":"https:\/\/kick-start.us\/it\/wp-json\/wp\/v2\/job-listings\/12785","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/kick-start.us\/it\/wp-json\/wp\/v2\/job-listings"}],"about":[{"href":"https:\/\/kick-start.us\/it\/wp-json\/wp\/v2\/types\/job_listing"}],"author":[{"embeddable":true,"href":"https:\/\/kick-start.us\/it\/wp-json\/wp\/v2\/users\/63"}],"wp:attachment":[{"href":"https:\/\/kick-start.us\/it\/wp-json\/wp\/v2\/media?parent=12785"}],"wp:term":[{"taxonomy":"job_listing_type","embeddable":true,"href":"https:\/\/kick-start.us\/it\/wp-json\/wp\/v2\/job-types?post=12785"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}