{"id":13380,"date":"2025-11-19T20:12:18","date_gmt":"2025-11-19T20:12:18","guid":{"rendered":"https:\/\/kick-start.us\/?post_type=job_listing&#038;p=13380"},"modified":"2025-11-19T20:12:18","modified_gmt":"2025-11-19T20:12:18","slug":"arkansas-398-engenheiro-de-projeto-asic","status":"publish","type":"job_listing","link":"https:\/\/kick-start.us\/pt-br\/vaga\/arkansas-398-engenheiro-de-projeto-asic\/","title":{"rendered":"Engenheiro de projeto ASIC"},"content":{"rendered":"<p>Descri\u00e7\u00e3o do cargo:<br \/>Location: Austin, Texas (Onsite \u2013 5 Days\/Week; Relocation Considered)<\/p>\n<p>Work Type: Full-Time, Permanent<\/p>\n<p>Experience Required: 5 \u2013 10 Years<\/p>\n<p>Compensation: USD 160,000 \u2013 180,000 (plus Equity)<\/p>\n<p>Eligibility: H1-B Sponsorship Available<\/p>\n<p>Job Overview<\/p>\n<p>Seeking an experienced VLSI RTL Designer to join a fast-growing, venture-backed semiconductor innovator developing next-generation programmable coherent DSP (Digital Signal Processing) solutions for AI infrastructure and cloud connectivity. The ideal candidate will contribute to designing high-performance communication systems from concept to silicon, collaborating with algorithm, verification, DFT, and physical design teams to deliver world-class semiconductor solutions.<\/p>\n<p>Principais responsabilidades<\/p>\n<ul>\n<li>Collaborate with Algorithm and Architecture teams to translate high-level requirements into efficient hardware implementations.<\/li>\n<li>Design and implement RTL for complex digital blocks using Verilog\/SystemVerilog\/VHDL.<\/li>\n<li>Participate in all design stages, including micro-architecture definition, synthesis, and timing analysis.<\/li>\n<li>Work with Verification teams to develop testbenches, debug issues, and achieve functional coverage closure.<\/li>\n<li>Partner with DFT engineers to ensure designs support scan insertion, ATPG, and BIST.<\/li>\n<li>Coordinate with Physical Design teams for floorplanning, timing closure, and routing optimization.<\/li>\n<li>Perform post-silicon or pre-silicon debug and analyze waveforms, assertions, and timing reports.<\/li>\n<li>Optimize for area, power, and performance (PPA) through iterative design improvements.<\/li>\n<li>Maintain accurate documentation for design specifications, interfaces, and design reviews.<\/li>\n<li>Contribute to IP\/SoC integration and system-level interface verification.<\/li>\n<li>Stay up-to-date with industry trends, EDA tools, and advanced verification methodologies.<\/li>\n<\/ul>\n<p>Must-Have Qualifications<\/p>\n<ul>\n<li>Minimum 5 years of experience as an ASIC\/VLSI Digital Design Engineer.<\/li>\n<li>Strong RTL coding proficiency in Verilog\/SystemVerilog\/VHDL.<\/li>\n<li>Hands-on experience with synthesis, timing analysis, and simulation environments.<\/li>\n<li>Sound understanding of DFT concepts \u2013 scan insertion, ATPG, and BIST.<\/li>\n<li>Proven ability to translate algorithmic concepts into optimized RTL.<\/li>\n<li>Solid knowledge of digital design fundamentals and ASIC development flow.<\/li>\n<li>Excellent collaboration and communication skills with cross-functional teams.<\/li>\n<li>On-site availability in Austin, TX (5 days per week).<\/li>\n<\/ul>\n<p>Nice-to-Have Qualifications<\/p>\n<ul>\n<li>Experience with Optical Communication Systems and Ethernet (100G and above).<\/li>\n<li>Background in DSP-oriented designs or high-speed serial interfaces.<\/li>\n<li>Experience in IP\/SoC integration and system-level debugging.<\/li>\n<li>Scripting proficiency in Python, Perl, or TCL.<\/li>\n<li>Strong interpersonal skills, self-starter attitude, and entrepreneurial mindset.<\/li>\n<li>BS\/MS in Electrical or Computer Engineering from a top university.<\/li>\n<\/ul>\n<p>Perks &amp; Benefits<\/p>\n<ul>\n<li>Competitive salary with meaningful equity participation.<\/li>\n<li>Full Medical &amp; Dental coverage.<\/li>\n<li>Opportunity to work on next-generation semiconductor technology powering AI and cloud infrastructure.<\/li>\n<li>Open to H1-B sponsorship.<\/li>\n<li>Dynamic startup culture with top-tier venture backing.<\/li>\n<li>Exposure to advanced EDA tools, architectures, and silicon bring-up activities.<\/li>\n<\/ul>","protected":false},"author":10,"featured_media":0,"template":"","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"pmpro_default_level":"","_promoted":"","_job_location":"Arkansas","_application":"https:\/\/visasponsor.jobs\/api\/jobs\/dddcc4e4ad734c1990e4bca13d7a0fce\/ASIC-Design-Engineer","_company_website":"","_company_tagline":"","_company_twitter":"","_company_video":"","_filled":0,"_featured":0,"_remote_position":0,"_job_salary":"","_job_salary_currency":"","_job_salary_unit":"","_joinchat":[]},"job-types":[398],"class_list":{"0":"post-13380","1":"job_listing","2":"type-job_listing","3":"status-publish","4":"hentry","5":"pmpro-has-access","7":"job-type-h1-b"},"_links":{"self":[{"href":"https:\/\/kick-start.us\/pt-br\/wp-json\/wp\/v2\/job-listings\/13380","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/kick-start.us\/pt-br\/wp-json\/wp\/v2\/job-listings"}],"about":[{"href":"https:\/\/kick-start.us\/pt-br\/wp-json\/wp\/v2\/types\/job_listing"}],"author":[{"embeddable":true,"href":"https:\/\/kick-start.us\/pt-br\/wp-json\/wp\/v2\/users\/10"}],"wp:attachment":[{"href":"https:\/\/kick-start.us\/pt-br\/wp-json\/wp\/v2\/media?parent=13380"}],"wp:term":[{"taxonomy":"job_listing_type","embeddable":true,"href":"https:\/\/kick-start.us\/pt-br\/wp-json\/wp\/v2\/job-types?post=13380"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}